BOOTSTRAP WORDLINE DRIVER DOWNLOAD

Therefore, as the tenth NMOS transistor N 10 of the second stage and the twelfth NMOS transistor N 12 of the third stage are turned on, the boosting voltage generating unit represents a different driving characteristic from the conventional bootstrap circuit. This voltage at node N1 is sufficient to turn off T1, even though node N1 is otherwise negative with respect to Vcc and would tend to turn on T1. This turns device 28 on but turns device 40 off. The circuit operates as follows. IR transmission diode, uses controlled switch for supplying voltage to voltage-controlled resistance providing driver current pulses.

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The doubled voltage appears at bootstgap other terminal of the capacitor, and this other terminal is connected directly to the circuit output. When the timing signals on leads and fall to GND, the node 36 goes high and turns device 34 off. It should be understood that the present invention is not limited to the illustrated wordline driver and decoder SRAM circuit with only one group of wordlines.

USB1 - Bootstrap circuit - Google Patents

The bootstrap unit 61, the clamping unit 62, the charge pump unit 63, the constant voltage producing unit 64 and the switching unit 65 are similar in arrangement to the corresponding units 31, 32, 30, 33 and 34 with the exception that a voltage level adjusting circuit 64b is coupled between the source of power voltage level Vcc and the controlling unit 66, and, for this reason, the component elements of those units 61 to 65 are labeled with the same references used in FIG.

After the time delay determined by the inverters throughnode 70 goes low and forces node 26 to high. Voltage bootstrap circuit and method for decoding low-voltage low-power consumption electrically erasable programmable read-only memory EEPROM row.

A voltage boosting clock circuit according to claim 4 further including a first logic gate having an output terminal connected to said gate electrode of said fifth transistor device and having a first input terminal connected to said source of timing signals at said second node, a first inverter circuit having an input botstrap connected to said source of timing signals at said second node and an output terminal connected bootsrtap a second input terminal of said first logic gate.

The negatively charged terminal is isolated from ground and reconnected to the positive power supply terminal.

Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations. Thus, the conventional bootstrap circuit has problems that not only a margin of the word wordine voltage could not be secured but also the target specification range could not be secured. However, if the node N31 is decayed from the power voltage level to the ground voltage level, NOR gate NR62 shifts the output signal from logic "0" level to logic "1" level, because the delay circuit DL62 retards the voltage rising at the output node of the inverting circuit IN62 and keeps one of the output nodes in logic "0" level.

The discharging of the load through device 32 and device 24 causes the node 26 to bump up.

US6559707B1 - Bootstrap circuit - Google Patents

The circuit of claim 5 wherein the latch nodes are connected only to the gates of said second and third FETs and to the drains of said second, third, fourth and fifth FETs, whereby said second, third, fourth and fifth FETs stop conducting after the capacitances of the latch nodes have been charged or discharged following a transition in the input signal.

The input of the inverter stage is connected to a node N2 explained later and its output is connected to node N3. If no leakage current takes place, not only the charge pump unit 30 but also the clamping unit 32 may be deleted from the bootstrap circuit according to the present invention. A capacitive load is connected to the node Voltage booster circuit using level shifter composed of two complementary MIS circuits.

In order to accomplish the above object, a boosting voltage generator according to the present invention is characterized in that it comprises a supply voltage level detection unit for detecting a high potential supply voltage and a potential supply voltage using a reference voltage; and a boosting voltage generator for controlling the level of a boosting voltage depending on bootstrp clamp signal generated by an output signal of the supply voltage level detection unit.

The voltage level at the output node N2 starts on decay at time t6 and is recovered to the low voltage level for blocking the storage capacitors from the associated bit lines. This results in that the extremely thin gate oxide films are liable to be damaged, and the clamping circuit 2 is useless.

Device 24 is now in a diode configuration. A bootstrap circuit as set forth in claim boottstrap, in which said bootstrap circuit further comprises a champing unit coupled to said output node for restricting said output voltage level to botstrap first predetermined volgate level.

While decaying the voltage level at the output node N2, wordlne clamping circuit 2 discharges the current from the output node N2 as useless charges. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. The circuit of claim 1 wherein the load is a word line in a semiconductor memory.

Static random access memory SRAM write assist circuit with leakage suppression and level control.

For this reason, the complementary input signal CSin thus lowered is supplied to one of the electrodes of the bootstrap capacitor C31, and accumulates the bootstrap capacitor C A bootstrap circuit as set forth in claim 5, in which said bootstrap circuit further comprises a charge pump unit coupled to the output node for supplementing electric charges.

Method for discharging word line and semiconductor memory device using the same.

The output signal HFVDD has the potential approximately same to the supply voltage Vcc and is increased in response to the supply voltage Vcc.

The gate of the FET is connected to a word line. A bootstrap circuit as set forth in bootsstrap 1, wherein the bootstrap unit is adapted to vary the voltage at the output node in proportion to the power voltage level. High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion.

The first NMOS transistor has its gate and drain connected together and forms a diode.

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme wit

After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. A need exists for a wordline voltage boosting circuit that efficiently and effectively boosts a voltage level for a wordline while minimizing required chip area to implement the wordline voltage boosting circuit.

The circuit of claim 1 wherein the latch comprises a second FET T2 and a third FET T3 having their gate and drain terminals cross connected bootstarp the first and second latch output nodes.