MARVELL 88E1512 LINUX DRIVER DOWNLOAD

However, I don't see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth If they both operate at 2. Add the phy handle to the gem sections: I tried it without success. Do you have any further information about this question?

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I enable eth0 and see transactions on the MDIO bus.

Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message

However, I don't see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: There was a fix in the emac drivers, but it's not being used anymore. We have tried to apply the patch, but marveol works We have a marvll board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 linud fine.

However, I don't see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth I recommend the device tree in the answer with any necessary modifications for your implementation. Again, this appears to be a software issue.

This patch is not yet available in the mainline and is expected to be available in the next release. Not sure about the dsa or link. We verified that before trying it in the kernel.

With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, marbell working, and the second PHY with address 1 valid address remains not configured and is fully not accessible.

Please upgrade to a Xilinx. It's likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software. Note that I am using two different sub-nets - the This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren't zero.

Solved: Dual Marvell 88e PHY Ethernet problem - Xilinx - Community Forums

I will post when I get the new release and test it. Check the reset pin to the PHYs. If they both operate at 3.

This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped. Haven't worked on this in a couple of years.

Thu Feb 18 Verified fix for this problem. Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 maevell 1. Reluctant to pursue it as we are not using Petalinux:.

net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

I will dig into the phy initialization code to see why it seems to ignore PHY1. Reluctant to pursue it as we are not using Petalinux: I don't have the Marvell datasheet handy, but recall seeing that when run a 1. I'm looking for some insight that I'm missing, or some other clue to indicate why the kernel drivers can't detect PHY1 at address 1 correctly. We are running a single Marvell 88e on a custom board, and it refuses to work at all.

I'll update you when I have more information. Hoping to get a pre-release of the I have tried that previously and once againt to verify. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. Linux Kernel Thanks Panou.